1. Field of the Invention
This invention relates to adaptive analog filters, particularly to monolithic integrated circuit implementation of a filter using a least mean square error algorithm.
2. Description of the Prior Art
One example of an adaptive filter is one that implements the least mean square (LMS) algorithm developed by Widrow and Hoff and described in a publication entitled "Adaptive Switching Circuits," in IRE WESCON Conv. Rec., pt. 4, p. 96, 1960. A modification of the least mean square algorithm developed by Widrow and Hoff was made by Moschner and was described in a publication entitled "Adaptive Filter with Clipped Input Data," Stanford Lab Report 6796-1, June 1970. Both Widrow and Hoff and Moschner provided an algorithm which simplified the calculation of the least mean square algorithm by eliminating the need to average data over a large number of samples and by retaining the polarity of the delayed input reference data to determine the direction of weight adjustment.
The least mean square algorithm is more complex to implement than a programmable analog transversal filter in that an input signal is sampled to provide a sequence of discrete signals or samples, each of which are weighted and summed to provide an output signal, the output signal is then subtracted from a desired signal to provide an error signal .epsilon..sub.m which is used to modify the value of the weight at each tap of a tapped delay line.
One example of a programmable analog transversal filter is described in U.S. Pat. No. 4,034,199 which was issued on July 5, 1977 to D. R. Lampe, M. H. White, and J. H. Mims and assigned to the assignee herein. In U.S. Pat. No. 4,034,199 a transversal filter is described comprising a charge coupled device for receiving a series of discrete analog signals to be delayed by increasing periods of time and having outputs from each stage of the charge coupled device coupled to MNOS transistors having variable thresholds for weighting the data at each tap location. The weighted output of each tap was summed in an integrator to provide an output signal. Means were provided to program the weights at each tap according to predetermined control signals.
An adaptive analog processor is a step further in complexity in that the weights for each tap are adjusted automatically with the arrival of each new sample of data by means of a recursive algorithm.
It is therefore desirable to implement through various techniques an adaptive analog processor on an integrated circuit chip.
It is further desirable to implement an adaptive analog processor utilizing charge transfer devices.
It is further desirable to implement an adaptive analog processor including means for concomitant updating of the weights at each tap location.
It is further desirable to provide means for applying positive as well as negative weights to each tap of a tapped delay line.
It is further desirable to provide means to compensate for direct current offsets in the tap multiplier weights, temperature drift of chip components, and long term drift of input analog signals through the use of a direct current bias tap weight.
It is further desirable to utilize a low power, high-speed, minimum area, integrated circuit technology, for example CMOS, to implement analog (e.g. operational amplifiers) and digital (e.g. clocks, drivers, etc.) functions on the chip.
It is further desirable to utilize a comparator, an exclusive OR and a digital tapped delay line to facilitate updating the weights at each tap location, thereby avoiding the requirement of a four-quadrant analog multiplier at each tap location.
It is further desirable to implement an adaptive analog processor utilizing an absolute value amplifier which may amplify either positive or negative signal values.
It is further desirable to implement an adaptive analog processor utilizing a charge coupled device delay line which is clocked with a 2 phase clock to increase the time the data is valid at each tap location.